Paging

As a told you in the previous section, a logical address is translated to a linear address. When paging is disabled, the linear address is mapped directly to the physical address space. Paging provides a further level of indirection. When paging is enabled (by switching the PG bit 31 in the CR0 register to '1'), the linear address space is split into pages of 4kB length. These pages can be present in physical memory or exported to disk storage. The translation from linear to physical address works via the page directory and page tables.

The physical address of the page directory is stored in the CR3 register.